Drive device for a brushless motor

ABSTRACT

A brushless motor driving device includes a plurality of motor driving coils and a plurality of driving transistors, coupled to the motor driving coils, for periodically supplying an electric power to the motor driving coils. A power supply switching circuit is provided for generating a power supply switching signal for driving the motor driving coils on the basis of a frequency signal corresponding to an oscillation frequency of a voltage controlled oscillator. A phase difference detector is provided for detecting a difference between the power supply switching signal and a counterelectromotive voltage generated in the motor driving coils during a period in which no electric power is supplied to the motor driving coils. The phase difference detected by the phase different detector circuit is used to control the oscillation frequency of the voltage controlled oscillator.

FIELD OF TECHNOLOGY

The present invention relates to a drive device for a brushless motorwhich does not make use of a position detector for detecting theposition of a movable element of an electric motor.

BACKGROUND ART

With a view to improving service life and reliability, the brushlessmotor is being largely employed for various drive motors. In general,the brushless motor requires the use of a position detector fordetecting the position of a movable element. However, in order tofurther reduce price and size, a brushless motor which does not requirethe use of a position detector is necessary. A conventional example of adrive device for such a brushless motor is disclosed in, for example,the Japanese Laid-open Patent Publication No. 52-80415.

Hereinafter, the above described conventional drive device for thebrushless motor will be discussed with reference to the drawings.

FIG. 17 is a circuit diagram of the conventional drive circuit for thebrushless motor. In FIG. 17, driving coils 1 to 3 are connected at theirone end to each other. The driving coil 1 is connected at the other endto the anode of a diode 4, the cathode of a diode 5 and the respectivecollectors of driving transistors 10 and 13. The driving coil 2 isconnected at the other end to the anode of a diode 6, the cathode of adiode 7 and the respective collectors of driving transistors 11 and 14.The driving coil 3 is connected at the other end to the anode of a diode8, the cathode of a diode 9 and the respective collectors of drivingtransistors 12 and 15. The respective cathodes of the diodes 4, 6 and 8and the respective emitters of the driving transistors 10, 11 and 13 areconnected to a positive power supply line, and the respective anodes ofthe diodes 5, 7 and 9 and the respective emitters of the transistors 13,14 and 15 are connected to ground. The other ends of the driving coils 1to 3 are also connected with a filtering circuit 16 which generates anoutput to a power supply switching circuit 17. An output from the powersupply switching circuit 17 is supplied t the respective bases of thedriving transistors 10 to 15.

The drive device for the brushless motor, which is so constructed ashereinabove described, operates in the following manner.

FIG. 18 is a diagram for explaining the operation of the device shown inFIG. 17, wherein Uo, Vo and Wo represent the respective waveforms of theelectric power signals supplied to the driving coils 1, 2 and 3. Thepower supply waveform Uo, Vo and Wo have their high harmonic componentsremoved by the filtering circuit 16 and are respectively converted bythe filtering circuit 16 into output signals F1, F2 and F3 which aredelayed 90° in phase. It is noted that the filtering circuit 16 is aprimary filter and is constituted by, for example, a RC passive filter,a primary Miller integrator, etc., the cut-off frequency of which is setto a sufficiently low region as compared with the frequencies of thepower supply waveforms across the coils. The output signals F1, F2 andF3 are inputted to the power supply switching circuit 17. The powersupply switching circuit 17 is constituted by a logic circuit and isadapted to logically process the output signals F1, F2 and F3 intocontrol signals U_(H), U_(L), V_(H), V_(L), W_(H) and W_(L) which are inturn are supplied to the bases of the driving transistors 10 to 15 tocause the latter to perform their respective switching operations. Atthis time, the switching operations are carried out so that a motordriving torque is generated in one direction at all times for driving amotor.

In the prior art construction, it is necessary to use a filteringcircuit having a cut-off frequency characteristic for each phase of thedriving coils and, accordingly, a number of capacitors having a highcapacitance is required.

Also, where the inductance of the driving coils is high, the powersupply current to be passed through the coils tends to be delayed intime after the driving transistors are switched on, and permanentmagnetic fields tend to be degaussed by magnetic fields generated by thedriving coils. A so-called armature reaction exists. In such case, it iswell known that, when the driving coils are supplied with an electricpower at such timings as shown in FIG. 18, the efficiency tends to belowered. As a countermeasure, a technique in which the signals F1, F2and F3 are somewhat advanced in phase to operate the driving transistorsso as to compensate for a delay in power supply resulting from thearmature reaction is disclosed in the Japanese Laid-open PatentPublication No. 52-80145, however, component parts, such as capacitors,are further required. Also, since the power supply waveforms Uo, Vo andWo tend to be accompanied by spike noises generated when the drivingtransistors are switched off, a variation in power source voltage, avariation in current attributable to a change in load, and so on, it isoften difficult to obtain accurately a power supply switching signaleven though the power supply waveforms Uo, Vo and Wo are inputted to thefiltering circuit. As a countermeasure, a system has been suggested suchas disclosed in the Japanese Patent Publication No. 59-36519.

However, the system using the filtering circuit for providing the powersupply switching signal from the power supply waveform for the drivingcoils basically has the following problem. That is, a voltage dropresulting from both the power supplied during the supply of electricpower to the driving coils and the internal impedances of the drivingcoils, a spike noise occurring immediately after the interruption of thepower supply, and so on, tend to be superimposed on a fundamental wave(counterelectromotive force) of the power supply waveforms of thedriving coils. Such a voltage drop and spike constantly vary with avariation in power source voltage and load. Accordingly, where the powersupply waveforms of the driving coils are filtered to provide the powersupply switching signal, an error tends to occur as a result of theabove described component, such as the voltage drop, spike, etc., whichis superimposed on the fundamental wave (counterelectromotive force) ofthe power supply waveforms while the latter constantly vary, and it istherefore difficult to accurately supply the electric power to thedriving coils.

In order to eliminate the above described conventional problems, variousmethods have been suggested to obtain the power supply switching signalaccurately, all of which are basically characterized in that adjustmentis effected in the periphery of the filtering circuit for maintaining ata constant value the difference in phase between the driving coilcounterelectromotive force and the power supply switching signal. Suchan adjustment is extremely cumbersome. Also, other than those necessaryfor the filtering circuit, a number of additional capacitors arerequired and, therefore, when the driving circuit is fabricated into anintegrated circuit, both the number of component parts to be connectedand the number of connection pins tend to increase, rendering the pricehigh. Also, a system wherein no filtering circuit is employed and,instead, the use is made of, for example, a microcomputer for digitallyproviding the power supply switching signal is disclosed in the JapaneseLaid-open Patent Publication No. 61-293191, which is relativelyexpensive.

As hereinbefore discussed, since the conventional drive device for thebrushless motor is constructed so that the filtering circuit is used toprocess the power supply waveforms of the driving coils to provide thepower supply switching signal having a predetermined phase relationshipto the position of the movable element, the switching signal beingutilized to sequentially energize the driving coils, it is not possibleto obtain an accurate power supply switching signal because of a voltagedrop in the driving coils resulting from the spike noises contained inthe power supply waveforms of the driving coils and the electric currentsupplied, a variation of the superimposed component resulting from thechange of the power source voltage and the load, the armature reactionand so on. Also, an increased number of capacitors having a highcapacitance is required for constructing the filtering circuit and, inparticular, when the driving circuit is to be fabricated in anintegrated circuit, both the number of component parts to be connectedand the number of connection pins tend to increase, rendering itdisadvantageous in terms of price.

In view of the foregoing, a system such as disclosed in the JapanesePatent Publication No. 61-3193 is suggested wherein thecounterelectromotive force generated in the driving coils is shaped asto its waveform and use is made of a phase sync loop (PLL) circuit togenerate an appropriate phase pulse to permit the driving coils to besequentially supplied with electric power to drive the motor. In otherwords, there is disclosed a system wherein, according to theconstruction shown in FIG. 19, counterelectromotive voltages A, B and Cgenerated by the driving coils are pulse-shaped and arithmeticallyprocessed to provide a pulse signal G which is compared in phase with adivider output I provided at an output of a voltage controlledoscillator, a thus compared output being fed back to the voltagecontrolled oscillator to make the signals I and G to be matched in phasewith each other so that the frequency division of the signal I canresult in a generation of the power supply signal for the driving coilsto thereby drive the motor. The behavior of the signals at variousportions of this system are shown in FIG. 20. However, in such a system,a voltage drop resulting from the electric current supplied during thesupply of the electric power to the driving coils and the internalimpedances of the driving coils, the spike noises generated immediatelyafter the interruption of the power supply, and so on, are superimposedon the counterelectromotive voltage generated in the driving coils ashereinbefore described and, therefore, it is extremely difficult toobtain the pulse signal by shaping and arithmetically processing thecounterelectromotive force generated in the driving coils. In fact, withthe construction shown in FIG. 19, it is not easy to obtain a pulsesignal G as shown in FIG. 20 and the spike noise generated immediatelyafter the power supply through the driving coils necessarily affects theoperation. Accordingly, it is impossible to accomplish the phasecomparison with the divider output I and, therefore, it is impossible torender the phases of the signals I and G to be matched with each other.

As hereinbefore discussed, the conventional drive devices for thebrushless motor have had various problems.

SUMMARY OF THE INVENTION

Accordingly, the object of the present invention is to provide a drivedevice for a brushless motor wherein the necessity of the use of anumber of capacitors having a high capacitance hitherto required in theconventional filtering circuit is eliminated and the sequential supplyof an electric power through the driving coils is possible without beingadversely affected by any possible effect brought about by spike noisescontained in the power supply waveform for the driving coils, by avariation in power source voltage, by a variation in load and by anarmature reaction.

The present invention includes a plurality of phases of motor drivingcoils; a plurality of driving transistors connected to the drivingcoils; a voltage controlled oscillator for outputting a signal having anappropriate frequency; a power supply switching circuit for forming apower supply switching signal for the driving coils on the basis of afrequency signal corresponding to the frequency of oscillation of thevoltage controlled oscillator; and a phase difference detector having acomparator for generating a phase difference detecting pulse having apredetermined phase relationship with the power supply switching signalduring a period in which no electric power is supplied to the drivingcoils, and also for comparing a counterelectromotive voltage generatedin the driving signals with a neutral point voltage of the driving coilsduring a period in which the phase difference detecting pulse isgenerated, the phase difference detector being operable to detect anequivalent phase difference between the power supply switching signaland the counterelectromotive voltage in reference to an output from thecomparator; and a difference amplifier for amplifying an output from thephase difference detector and for generating an output which is in turnapplied to the voltage controlled oscillator.

Since this construction forms a feedback loop, that is, a phasecontrolled loop (PLL loop) wherein the phase difference between thecounterelectromotive voltage generated in the motor driving coils andthe power supply switching signals for the driving coils is detected sothat the frequency and phase of the power supply switching signal can becontrolled in dependence on the detected phase difference to therebypermit the power supply switching signal to exhibit a predeterminedphase relationship with the position of the movable element, the use ofthe filtering circuit hitherto required can be dispensed with, andaccordingly, all inconveniences brought about by the use of thefiltering circuit can be advantageously eliminated.

Also, since the difference in phase between the counterelectromotivevoltage generated in the motor driving coils and the power supplyswitching signal for the motor driving coils is detected during theinterruption of the power supply, an accurate detection of the phasedifference is possible and the phase controlled loop can be steadilyoperated.

Also, the present invention includes a plurality of phases of motordriving coils; a plurality of driving transistors connected to thedriving coils; a power supply switching circuit for sequentiallytransmitting a power supply switching signal for the driving coils tothe driving transistors; a reference signal generator for inputting asignal having an appropriate frequency to the power supply switchingcircuit; a phase difference detector for detecting a phase differencebetween the counterelectromotive voltage generated in the driving coilsand the power supply switching signal for the driving coils during theinterruption of the power supply to the driving coils; and a differenceamplifier for amplifying an output from the phase difference detector,an output of said the difference amplifier being used as a torquecommanding signal.

Since this construction forms a feedback loop, that is, a phasecontrolled loop wherein the phase difference between thecounterelectromotive voltage generated in the motor driving coils andthe power supply switching signal for the driving coils that issynchronized with an output from the reference signal generator isdetected so that a motor driving torque can be controlled in dependenceon the detected phase difference with the counterelectromotive voltagefor the driving coils having a predetermined phase relationship with theoutput from the reference signal generator, a speed control and a driveof the brushless motor are possible without using the position detectorfor the movable element hitherto required and, therefore, the abrushless motor which is compact, low in price, high in reliability, andso, can be realized.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing a drive device for a brushless motoraccording to one embodiment of the present invention;

FIGS. 2A, 2B and 2C are explanatory diagrams for explaining theprinciple of operation of the circuit of FIG. 1;

FIG. 3 is a detailed circuit diagram of a phase difference detectingpulse generator;

FIG. 4 is an explanatory diagram for explaining the operation of thecircuit of FIG. 3;

FIG. 5 is a detailed circuit diagram of a phase difference detector;

FIG. 6 is an explanatory diagram for explaining the operation of thecircuit of FIG. 5;

FIG. 7 is a diagram showing operative waveforms in one embodiment of thepresent invention;

FIG. 8 is a detailed circuit diagram of a voltage controlled oscillatorand a lowest frequency setting circuit;

FIG. 9 is a detailed circuit diagram of a difference amplifier and adifference amplifier output clamping circuit;

FIG. 10 is a detailed circuit diagram of a phase difference detectingpulse generator and a pulse timing selecting circuit;

FIG. 11 is a detailed circuit diagram of the difference amplifier outputclamping circuit and a resetting circuit;

FIG. 12 is a circuit diagram of a drive device for a brushless motoraccording to a second embodiment of the present invention;

FIG. 13 is a circuit diagram of the drive device for the brushless motorin one embodiment of the present invention;

FIGS. 14A, 14B and 14C are diagrams showing the principle of operationof the circuit shown in FIG. 13;

FIGS. 15 and 16 are circuit diagrams of the drive device for thebrushless motor according to other embodiments of the present invention,respectively;

FIG. 17 is a circuit diagram of the conventional drive device for thebrushless motor;

FIG. 18 is a diagram for explaining the operation of the conventionaldrive device for the brushless motor;

FIG. 19 is a circuit diagram showing a different conventional drivedevice for the brushless motor; and

FIG. 20 is a diagram for explaining the operation of the circuit of FIG.19.

BEST MODE OF CARRYING OUT THE INVENTION

Hereinafter, a drive device for the brushless motor in one embodiment ofthe present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a drive device for a brushless motoraccording to one embodiment of the present invention. In FIG. 1, likereference numerals are employed to denote like parts which are identicalin function with those of the conventional drive device for thebrushless motor shown in FIG. 17 and, therefore, the details thereofwill not be described. In FIG. 1, the respective bases of the drivingtransistors 10 to 15 are connected to outputs of a power amplifier 43which has inputs connected to respective outputs of a logic circuit 42.The logic circuit 42 and the power amplifier 43 together constitute apower supply switching signal generator 44. The logic circuit 42 has aninput connected to an output D1 of a frequency divider 41 which has aninput connected with an output of a voltage controlled oscillator 40. Tothe voltage controlled oscillator 40 is connected a lowest frequencysetting circuit 50. Outputs D1, D2 and D3 from the frequency divider 41and outputs U1, U2, C1, V2, W1 and W2 from the logic circuit 42 areinputted to a phase difference detecting pulse generator 28, and endsUo, Vo and Wo of the respective driving coils 1, 2 and 3 are inputted tobuffer circuits 21, 22 and 23. Respective outputs U_(B), B_(B) and W_(B)from the buffer circuits 21, 22 and 23 are inputted to a comparator 27and are connected together through resistors 24, 25 and 26, a commonjunction N_(B) being inputted to the comparator 27. An output PD of thecomparator 27 is controlled by an output from the phase differencedetecting pulse generator 28. The timing at which a phase differencedetecting pulse is generated from the phase difference detecting pulsegenerator 28 is set by a pulse timing selecting circuit 29. It is notedthat the various component parts 21 to 29 constitute a phase differencedetector 20 while the output PD constitutes an output from the phasedifference detector 20. The output PD from the phase difference detector20 is connected to an inverting input terminal of an operationalamplifier 31 through a resistor 32, and a series circuit of resistor 33and capacitor 34 and a capacitor 35 are connected between the invertinginput terminal of the operational amplifier 31 and an output terminalthereof. A non-inverting input terminal of the operational amplifier 31is applied with a predetermined bias voltage from resistors 36 and 37.It is noted that the various component parts 31 to 37 constitute adifference amplifier 30 while an output EAO from the differenceamplifier 30 is connected to an input of the voltage controlledoscillator 40.

Also, the difference amplifier 30 is connected to a difference amplifieroutput clamping circuit 53.

The inverting input terminal of the operational amplifier 31 and anoutput of the difference amplifier output clamping circuit 53 areinputted to a reset circuit 60 whose output is used to control theoutput PD of the comparator 27.

Another output D4 of the frequency divider 41 is inputted to the base ofa transistor 200 having its emitter connected to ground and itscollector connected to a stabilizing power source line through aresistor 201 and also to a speed signal output terminal 202.

The operation of the drive device for the brushless motor which is soconstructed as hereinabove described will now be described.

FIG. 2 is an explanatory diagram for explaining the principle ofoperation of the present invention, showing a phase relationship betweena driving coil counterelectromotive voltage and a driving coil powersupply waveform. FIG. 2(a) illustrates the case in which the phaserelationship between the counterelectromotive voltage (dotted line) andthe power supply waveform (solid line) is optimum, whereas FIGS. 2(b)and 2(c) illustrate the respective cases wherein a displacement of aphase angle ψ occurs from the optimum condition. In FIG. 1, the outputfrom the voltage controlled oscillator 40 is transmitted to the drivingcoils 1 to 3 through the frequency divider 41, thepower supply switchingcircuit 44 and the driving transistors 10 to 15. Accordingly, the outputfrom the voltage controlled oscillator 40 and the power supply waveformsfor the driving coils 1 to 3 have a predetermined phase relationship. Inother words, by controlling the oscillating frequency and phase of thevoltage controlled oscillator 40, it is possible to control a differencein phase between the driving coil counterelectromotive voltage and thedriving coil power supply waveform. In view of this, if a phase controlloop is provided in which, where as shown in FIGS. 2(b) and 2(c) thedisplacement of the phase angle ψ occurs between the driving coilcounterelectromotive voltage and the driving coil power supplywaveforms, the phase difference ψ is detected by the phase differencedetector 20 and then amplified by the difference amplifier 30 and theoscillating frequency and phase of the voltage controlled oscillator 40can be controlled so as to render ψ to become zero, it is possible tosecure the optimum power supply condition shown in FIG. 2(a).Accordingly, it is possible to steadily and efficiently generate a motordriving torque and the motor is thus driven.

The specific construction of the phase difference detector 20 will nowbe described in detail.

Such a circuit as shown in FIG. 3 can be contemplated by way of exampleas a specific construction of the phase difference detecting pulsegenerator 28 in the phase difference detector 20. In FIG. 3, componentswhich are similar in function to those shown in FIG. 1 are designated bylike reference numerals. The outputs U1, U2, V1, V2, W1 and W2 of thelogic circuit 42 and the outputs D1, D2 and D3 of the frequency divider41 are applied to the phase difference detecting pulse generator asrespective input signals. FIG. 4 is an explanatory diagram for use inexplaining the operation of the phase difference detecting pulsegenerator shown in FIG. 3, wherein the waveforms shown in FIG. 4correspond to those of signals appearing at respective points shown byassociated symbols in FIG. 3. Output terminals S0, S1, S2, S3, S4, S5and S6 of the phase difference detecting pulse generator 28 providerespective signal waveforms designated in FIG. 4 by the same symbols asused in FIG. 3.

Then, as a specific construction of the phase difference detector 20including the phase difference detecting pulse generator 28, such acircuit as shown in FIG. 5 can be contemplated by way of example. InFIG. 5, components which are similar in function to those shown in FIG.1 are designated by like reference numerals. Specifically, ends Uo, Voand Wo of the driving coils 1, 2 and 3 are inputted to the respectivebuffer circuits 21, 22 and 23 which have their outputs U_(B), V_(B) andW_(B) connected together at the common junction N_(B) which is in turnis connected to inverting input terminals of comparators 100, 120 and140 and non-inverting input terminals of comparators 110, 130 and 150.The output U_(B) of the buffer circuit 21 is connected to anon-inverting input terminal of the comparator 100 and an invertinginput terminal of the comparator 110; the output V_(B) of the buffercircuit 22 is connected to a non-inverting input terminal of thecomparator 120 and an inverting input terminal of the comparator 130;and the output W_(B) of the buffer circuit 23 is connected to anon-inverting input terminal of the comparator 140 and an invertinginput terminal of the comparator 150. Outputs from the comparators 100,110, 120, 130, 140, and 150 the collector outputs from respective outputtransistors 101, 111, 121, 131, 141 and 151 are connected together andare in turn connected to a collector of a transistor 161, therebyconstituting a phase difference detector output PD. The base of thetransistor 161 is connected to the base and collector of a transistor162 and also to the collector of a transistor 164 and the collector of atransistor 169 which operates as a constant current source. The emitterof the transistor 162 is applied with a stabilizing power source voltageVreg through a resistor 163 and the emitters of the transistors 161 and164 are applied with the stabilizing power source voltage Vreg. The baseof the transistor 164 is connected to the emitter thereof through aresistor 166 and also through a resistor 165 with the collector of atransistor 167 whose emitter is grounded. The base of the transistor 167is connected through a diode 168 with an output S0 of the phasedifference detecting pulse generator 28. Other outputs S1, S2, S3, S4,S5 and S6 of the phase difference detecting pulse generator 28 areconnected through resistors 171, 173, 175, 177, 179 and 181 with thebases of emitter-grounded transistors 170, 172, 174, 176, 178 and 180,respectively, and the collectors of the transistors 170, 172, 174, 176,178 and 180 are connected with the bases of the transistors 101, 111,121, 131, 141 and 151, respectively. Input terminals of the phasedifference detecting pulse generator 28 are connected with the outputsU1, U2, V1, V2, W1 and W2 of the power supply switching circuit 44 andthe outputs D1, D2 and D3 of the frequency divider 41.

With respect to the phase difference comparator so constructed ashereinabove described, the operation thereof will be describedhereinafter.

FIG. 6 is an explanatory diagram for explaining the operation of thephase difference comparator and illustrates how the phase differencebetween the counterelectromotive voltage and the power supply waveformis detected as far as the driving coil 1 is concerned. In FIG. 6, thedriving coil 1 is supplied with signals U1 and U2 (that is, U_(H) andU_(L)), as power supply commanding signals, which are synchronized withD1 and D3 which are frequency-divided outputs of the voltage controlledoscillator 40. Accordingly, a period during which both of U1 and U2 arenot outputted is a power supply interrupting period and, during thisperiod, the driving coil power supply waveform Uo coincides with thecounter-electromotive voltage Ue. From FIG. 6, the power supplyinterrupting period corresponds to a period from the time at which U2 isrendered to be Low to the time at which U1 is rendered to be High andcorresponds to one clock of D1 or four clock periods of D3. Althoughthere exists the power supply interrupting period even during a periodfrom the time at which U2 is rendered to be Low to the time at which U1is rendered to be High, only the former period will be taken intoconsideration for the purpose of simplification of the description.During the power supply interrupting period, comparing a neutral pointvoltage No of each driving coil with the driving coil power supplywaveform Uo, when the phase difference ψ between Uo and the driving coilcounterelectromotive voltage Ue is zero, No and Uo coincide with eachother during the two clock periods of D3 subsequent to the time at whichthe center, that is, U1 is rendered to be Low during the power supplyinterrupting period. Also, where Uo is delayed a phase difference ψrelative to Ue, No and Uo coincide with each other before 2 clockperiods of D3 passes subsequent to the time at which U1 is rendered tobe Low, and, where Uo is advanced a phase difference ψ relative to Ue,No and Uo coincide with each other after two clock periods of D3subsequent to the time at which U1 is rendered to be Low. Accordingly,by comparing Uo and No with each other during two clock periods of D3subsequent to the time at which U1 become Low, the phase relationshipbetween Uo and Ue can be ascertained. Therefore, as a method for thedetection of the phase difference ψ, the comparator output PD having aduty corresponding to the phase difference ψ can be obtained bygenerating phase difference detecting pulse signals S2 and S0 having anappropriate width at a timing two clock periods of D3 subsequent to thetime at which U1 becomes Low and then by comparing No and Uo with eachother only when S2 and S0 are generated. In FIG. 6, there is shown thecase in which a period of ±0.5 clock period of D3 is generated two clockperiods of D3 subsequent to the time at which U1 becomes Low and Uo isdelayed relative to Ue by the phase angle ψ.

Although, in the foregoing, with respect to the detection of the phasedifference ψ utilizing the power supply interrupting period of the powersupply waveform Uo for the driving coil 1 from the timing at which U1becomes Low to the timing at which U2 becomes High, the principle ofoperation thereof has been described, a similar detection is alsopossible during the other power supply interrupting period relative toUo, that is, the period from the timing at which U2 becomes Low to thetiming at which U1 becomes High, as well as in the power supplywaveforms Vo and Wo of the other driving coils 2 and 3 and, therefore,in the illustrated embodiment, all of them are combined to provide thephase difference detector output PD.

Also, each of the buffer circuits 21, 22 and 23 is an invertingamplifier having a half (1/2) gain and arrangement is made so as topermit the outputs U_(B), V_(B) and W_(B) of the respective buffercircuits 21, 22 and 23 to fall within an operating input voltage rangeof each of the comparators 100, 110, 120, 130, 140 and 150.

FIG. 7 shows operating waveforms at various portions in the case wherethe phase difference detector 20 employed in FIG. 1 is of theconstruction shown in FIG. 5, illustrating the manner in which theoscillating frequency f of the voltage controlled oscillator 40 iscontrolled so as to render the phase difference between the driving coilpower supply waveform and the counterelectromotive voltage to be zero.

Hereinafter, the lowest frequency setting circuit 50 shown in FIG. 1will be described. The lowest frequency setting circuit 50 is operableto set the oscillating frequency of the voltage controlled oscillator 40to the lowest frequency at the time of starting the motor so that arevolving magnetic field of a speed sufficient to permit the movableelement to follow can be generated to assure the start of the motor. Ifthe counterelectromotive voltage is generated in the motor driving coilsas a result of the start of the motor, it is drawn into the previouslydescribed phase control loop and the motor is driven.

As a specific construction of each of the voltage controlled oscillator40 and the lowest frequency setting circuit 50, such a circuit as shownin FIG. 8 as a contemplated example. In FIG. 8, reference numeral 40represents the voltage controlled oscillator and reference numeral 50represents the lowest frequency setting circuit. In FIG. 8, the outputEAO of the difference amplifier 30 is connected to one input terminal ofa differential amplifier 461 through a resistor 460 and also to theemitter of a transistor 462. Another input terminal of the differentialamplifier 461 is connected to a dividing point of a voltage dividercomprised of resistors 463 and 464 connected between the stabilizingpower source line and ground. A difference between the two inputs of thedifferential amplifier 461 is amplified and inputted to the base of thetransistor 462. The collector of the transistor 462 is connected to thecollector and base of a transistor 465. The transistors 465 andtransistors 466 and 467 have their bases connected together and theiremitters grounded to provide a current mirror circuit. Transistors 468and 469 whose emitters are connected with the stabilizing power sourceline have their bases connected together and also to the collectors ofthe respective transistors 468 and 466. The collector of the transistor468 is connected to the collector of the transistor 467 and also to oneinput terminal of a comparator 470. A capacitor 471 is connected betweenthis one input terminal of the comparator 470 and ground. A resistor 473is connected between the collector of an output transistor 472 of thecomparator 470 and the other input terminal of the comparator 470. Aterminal of the resistor 473 adjacent this other input terminal of thecomparator 470 is connected to a bias power source 475 through aresistor 474. The collector of the transistor 472 is connected to thecollector of a transistor 478 for providing a constant current and alsowith the base of a transistor 477 through a resistor 476. The emitter ofthe transistor 477 is connected to the stabilizing power source line anda resistor 480 is connected between the base and the emitter thereof,the collector being connected to a common junction between therespective bases of the transistors 468 and 469.

The voltage of the bias power source 475 is divided by the dividingcircuit comprised of resistors 582 and 583, the voltage dividing pointbeing connected to one input terminal of a differential amplifier 581while the emitter of an output transistor 585 of the differentialamplifier 581 is connected to ground through a resistor 584 and also toanother input terminal of the differential amplifier 581. The transistor585 is of a multi-collector type and 1/4 of the collectors of thetransistor 585 is connected to the base of a collector-groundedtransistor 588 and also to the collector of a transistor 586. The baseof the transistor 586 is connected to the base of a transistor 587 andalso to the emitter of the transistor 588. The respective emitters ofthe transistors 586 and 587 are connected to the stabilizing powersource line. The collector of the transistor 587 is connected to thecollector of the transistor 462.

With respect to the voltage controlled oscillator 40 and the lowestfrequency setting circuit 50 which are so constructed as hereinabovedescribed, the operation thereof will now be described.

Assuming that in the difference amplifier 30 of FIG. 1 a voltage dividercomprised of resistors 36 and 37 is connected between the stabilizingpower source Vreg and ground and that the resistors 36 and 37 are ofequal resistance, the voltage value of the output EAO of the differenceamplifier 30 immediately after the power has been turned on will beVreg/2. Also, assuming that in the voltage controlled oscillator 40 ofFIG. 8 the resistors 463 and 464 connected to the input terminal of thedifferential amplifier 461 are of equal resistance, since the voltagevalue at the input terminal is Vreg/2, the voltage value at the junctionbetween another input terminal of the differential amplifier 461 and theemitter of the transistor 462 will be Vreg/2. Accordingly, immediatelyafter the power has been turned on, no voltage drop occur across theresistor 460. In other words, no current flow through the transistor462.

Now, the lowest frequency setting circuit 50 will be described. Assumingthat the voltage value of the bias power source 475 is V₇₅ and therespective resistances of the resistors 582, 583 and 584 are R₈₂, R₈₃and R₈₄, the voltage value at one input terminal of the differentialamplifier 581 will be V₇₅.R₈₃ /(R₈₂ +R₈₃). Since the other inputterminal of the differential amplifier 581 is in a condition toestablish an imaginal shortcircuit with such the one input terminal, thejunction between such other input terminal and the emitter of thetransistor 585 is equal to the voltage value V₇₅.R₈₃ /(R₈₂ +R₈₃) at theone input terminal. Accordingly, the emitter current of the transistor586 will be V₇₅.R₈₃ /{R₈₄.(R₈₃ +R₈₃)}. By way of the multi-collectorconstruction of the transistor 585 and the current mirror constituted bythe transistors 586 and 587, 1/12 of the emitter current of thetransistor 585, that is, V₇₅.R₈₃ /{12.R₈₄.(R₈₂ +R₈₃)}, is supplied tothe voltage controlled oscillator 40 as a collector current I₈₇ of thetransistor 587 to set it to the lowest frequency.

Hereinafter, how the oscillating frequency of the voltage controlledoscillator 40 is determined will now be described. When no charge ispresent on the capacitor 471 connected between one input terminal of thecomparator 470 and ground, the transistors 490 and 491 are switched onand off, respectively, and accordingly, the output transistor 472 of thecomparator 47 is switched off which in turn causes the transistor 477 tobe switched off with the consequence being that the current mirrorcircuit comprised of the transistor 468 and 469 is operated. The currentmirror circuit comprised of the transistors 465, 466 and 467 is operatedon the basis of the current flowing through the transistor 465.Accordingly, the capacitor 471 is charged by a current corresponding tothe difference between the collector current of the transistor 469 andthe collector current of the transistor 467. At this time, the voltageVj at the other input terminal of the comparator 470 is equal to thevalue shown by the following equation if a saturated voltage between theemitter and the collector of the transistor 478 is neglected.

    Vj=V.sub.75 +R.sub.74.(Vreg-V.sub.75)/(R.sub.73 +R.sub.74)

wherein Vreg represents the voltage of the stabilizing power source andR₇₃ and R₇₄ represent respective resistances of the resistors 473 and474. When, with the progress of the charging on the capacitor 471, thevoltage across the capacitor 471, that is, the voltage at one inputterminal of the comparator 470, increases to a value higher than thevoltage Vj, the transistors 490 and 491 are switched off and on,respectively, and accordingly, the transistor 472 is switched on whichin turn causes the transistor 477 to be switched on, with theconsequence being that the current mirror circuit comprised of thetransistors 468 and 469 is switched off. Therefore, the capacitor 471 ischarged by the collector current of the transistor 467. At this time,the voltage Vk at the other input terminal of the comparator 470 is of avalue equal to V₇₅.R₇₃ /(R₇₃ +R₇₄) if the saturated voltage between theemitter and the collector of the transistor 472 is neglected. When, withthe progress of the charging on the capacitor 471, the voltage acrossthe capacitor 471, that is, the voltage at one input terminal of thecomparator 470, decreases to a value lower than the voltage Vk, thecomparator 470 is inverted and the charging on the capacitor 471 isagain initiated. By repeating the cycle of charging and discharging ofthe capacitor 471 in this way, an oscillating waveform of a frequencycorresponding to the cycle of repeated charging and discharging can beoutputted from the collector of the output transistor 472 of thecomparator 470.

The oscillating frequency is determined by the magnitude of the chargingand discharging current of the capacitor 471 since the voltages Vj andVk are constant. In other words, when the charging and dischargingcurrent increase, the voltage across the capacitor 471 sets up and,since the set-up tends to become steep, the oscillating frequencybecomes high and, conversely, when the charging and discharging currentdecreases, the oscillating frequency becomes low. On the other hand, themagnitude of the charging and discharging current is determined on thebasis of the current flowing through the transistor 465. Also, thecurrent flowing through the transistor 465 corresponds to the sum of thecollector current I₈₇ of the output transistor 587 of the lowestfrequency setting circuit 50 and the collector current I₆₂ of the outputtransistor 462 of the differential amplifier 461.

Since, as hereinbefore described, the collector current I₆₂ of thetransistor 462 is zero immediately after the power has been turned on,the current flowing through the transistor 465 is equal to the currentI₈₇ from the lowest frequency setting circuit 50. Accordingly, theoscillating frequency of the voltage controlled oscillator 40 starts itsoscillation at the lowest frequency determined by the current I₈₇. Ifthis lowest frequency is adjusted to a value which is sufficient topermit the movable element of the motor to follow sufficiently, it ispossible to assuredly start the motor as a synchronous motorsynchronized with a frequency corresponding to the lowest frequency. Forthis purpose, the lowest frequency can be adjusted by rendering theresistance of the resistor 584 to be variable to vary the current I₈₇.Once the motor is started, the counterelectromotive voltage is generatedin the motor driving coil. Then, the phase difference between thecounterelectromotive voltage and the power supply switching signal forthe driving coils during the power supply interrupting period of thedriving coils is detected by the phase difference detector 20, and adirect current voltage corresponding to the phase difference so detectedis generated at the output EAO of the difference amplifier 30. Since thedirect current voltage is applied to one end of the resistor 460 and, onthe other hand, the other end of the resistor 460 is maintained atVreg/2 as hereinbefore described, a current corresponding to thedifference between the voltages at the opposite ends of the resistor 460flows through the transistor 462. Accordingly, a current equal to thesum of the current I₈₇ from the lowest frequency setting circuit 50 andthe collector current I₆₂ of the transistor 462 flows through thetransistor 465 and, therefore, the oscillating frequency of the voltagecontrolled oscillator 40 increases. In this way, in response to thedifference in phase between the counterelectromotive voltage in thedriving coils and the power supply switching signal, the output EAO ofthe difference amplifier 30 varies to control the oscillating frequencyof the voltage controlled oscillator 40.

The difference amplifier output clamping circuit 53 shown in FIG. 1 willnow be described.

The difference amplifier output clamping circuit 53 is operable to clampthe output from the difference amplifier 30 to speed up thephase-synchronized pull of the phase controlled loop at the time ofstarting the motor. In other words, by clamping and holding the outputEAO of the difference amplifier 30 at a level at which the oscillatingfrequency of the voltage controlled oscillator 40 starts its increase,it is possible to smoothly transmit a change in output PD of the phasedifference detector 20 as a change in oscillating frequency f of thevoltage controlled oscillator during a period from the start to thestanding and, accordingly, the phase-synchronized pull of the phasecontrolled loop can be speeded up with the motor consequently driven.

As a specific construction of the difference amplifier output clampingcircuit 53, such a circuit as shown in FIG. 9(a) is contemplated.Referring now to FIG. 9(a), a reference power source 51 operates as alevel clamp for the output EAO of the difference amplifier 30; acomparator 52 compares the output EAO of the difference amplifier 30with an output V₅₁ of the reference power source 51 for detecting a dropof the output EAO down to the level of V₅₁ so that an inverting input ofthe operational amplifier 31 can be controlled to avoid the drop of EAOdown to a level lower than the level of V₅₁. Thereby, the drop level ofEAO can be restricted to the level of V₅₁. The level of V₅₁ is the levelat which the oscillating frequency f of the voltage controlledoscillator 40 starts its increase and, when EAO is clamped at V₅₁, f isequal to the frequency fmin set by the lowest frequency setting circuit.However, f starts its increase when EAO is slightly higher than V₅₁. Byclamping, that is, holding, the EAO output at such a level V₅₁, it ispossible to transmit the change of the output PD at the start as thechange of f and, the quick synchronized pull (to establish asynchronized condition) of the phase controlled loop is possible.

It is noted that, although the clamping level for EAO has been set to beV₅₁, the clamping may be effected about V₅₁ -ΔV (ΔV=some dozen mV) inconsideration of offsets and others of various circuit components.

The relationship between the output EAO and the oscillating frequency fis shown in FIG. 9(b).

In FIG. 9(b), V₅₁ represents the clamping level at which the output EAOis clamped, and fmin represents the lowest oscillating frequency by thelowest frequency setting circuit.

The pulse timing selecting circuit 29 shown in FIG. 1 will behereinafter described.

In the circuit construction of the driving device for the brushlessmotor according to the embodiment of the present invention shown in FIG.1, it is assumed that the bias at the non-inverting input terminal ofthe difference amplifier 30 is set to Vreg/2. During a condition inwhich the output from the difference amplifier 30 is not saturated andthe phase controlled loop is operating steadily, the inverting inputterminal of the difference amplifier 30 is similarly Vreg/2 since it isin a condition to establish an imaginal shortcircuit with thenon-inverting input terminal thereof. The output PD of the phasedifference detector shown in FIG. 5 represents such a waveform as shownby PD in FIG. 6, that is, a waveform which operates at a High levelbeing Vreg and a Low level being zero. Under the condition in which thephase controlled loop is operating steadily, the PD waveform showntherein is controlled to represent a pulse waveform having an averagevoltage of Vreg/2, that is, a duty ratio of 50% High level and 50% Lowlevel. However, during the power supply interrupting period, comparingthe neutral point voltage No with the driving coil power supply waveformUo, the point of intersection between No and Uo when the phasedifference ψ between Uo and the driving coil counterelectromotivevoltage Ue is zero coincides at the center of the power supplyinterrupting period, that is, 2 clock periods of D3 subsequent to thetime at which U1 becomes Low and, therefore, in reference to the time 2clock periods of D3 subsequent to the time at which U1 becomes Low, thephase difference detecting pulses S2 and S0 are generated during a ±0.5clock period and, during this period, Uo and No are compared so that theduty of PD can be determined depending on the relationship in magnitudebetween Uo and No. Accordingly, the duty will become 50% High level and50% Low level and, therefore, the phase controlled loop can bestabilized. In other words, it is possible for the phase controlled loopto operate in a stabilized manner when the phase difference ψ between Ueand Uo is zero.

On the other hand, while the foregoing is based on the fact that thepoint of intersect between No and Uo during the power supplyinterrupting period lies intermediate of such a period, it is assumedthat the point of intersection between No and Uo deviate from the pointintermediate of the power supply interrupting period as a result of theoccurrence of a distortion in the driving coil power supply waveform Uo,that is, the counterelectromotive voltage waveform Ue by reason of, forexample, the relationship in gaussing pattern of a rotary magnet. Insuch a case, if as is the foregoing case the phase difference detectingpulses S2 and S0 are generated during ±0.5 clock period at a timing 2clock periods of D3 subsequent to the time at which U1 becomes Low andcomparison is made between Uo and No during such a period, the duty ofthe PD waveform deviates from the condition of 50% High level and 50%Low level and, therefore, a feedback is effected to the input of thevoltage controlled oscillator 40 through the difference amplifier 30 forthe purpose of compensating for the deviation. As a result thereof, inthe form as having a phase difference corresponding to the abovedescribed deviation between Ue and Uo the duty of the PD waveform willbecome 50% High level and 50% Low level and the phase controlled loopcan be stabilized. In other words, the timing of power supply switchingfor the driving coils relative to the counterelectromotive voltage inthe driving coils will be deviated from an optimum efficient point. Inorder to alleviate such a phenomenon, arrangement has been made suchthat the timing of generation of each of the phase difference detectingpulses S1 to S6 and S0 can be set by the pulse timing selecting means29.

As a specific construction of the pulse timing selecting circuit 29,such a circuit as shown in FIG. 10 in which it is shown together withthe phase difference detecting pulse generator 28 is contemplated by wayof example. In FIG. 10, like reference numerals are employed to denotelike parts which are identical in function with those shown in FIG. 1.The outputs U1, U2, V1, V2, W1 and W2 of the logic circuit 42 and theoutputs D1, D2 and D3 of the frequency divider 41 are applied as inputsignals to the phase difference detecting pulse generator. Referencenumeral 29 represents the pulse timing selecting circuit 29 forselecting and setting the timing at which the phase difference detectingpulses are generated. Either one of High, Middle and Low signals isinputted to an input terminal PT, and in correspondence with the inputsignals, a combination of signals Y0, Y1 and Y2 is determined. Then,arrangement has been made such that depending on the combination one ofswitches Z0, Z1 and Z2 in each of switch blocks 291 to 296 can beswitches on while the remaining two switches can be switched off.

Assuming that the High, Middle and Low signals inputted to the inputterminal PT are expressed by H, M and L, respectively, and the High andLow signals at terminals p and q and the terminals Y0, Y1 and Y2 areexpressed by H and L, respectively, the states of the signals at each ofthe above described terminals and those of the switches Z0, Z1 and Z2can be summarized as shown in the following table.

    ______________________________________                                        PT     p      q      Yo   Y1   Y2   Zo    Z1    Z2                            ______________________________________                                        H      L      L      H    L    L    ON    OFF   OFF                           M      L      H      L    H    L    OFF   ON    OFF                           L      H      H      L    L    H    OFF   OFF   ON                            ______________________________________                                    

It is noted that the switches Z0, Z1 and Z2 are switches on and off whenthe signals at the terminals Y0, Y1 and Y2 are High and Low,respectively.

In this way, depending on the respective states of the signals at theinput terminal PT of the pulse timing selecting circuits 29, theswitches Z0, Z1 and Z2 are selectively switches on and off so that thetiming at which the phase difference detecting pulses S1 to S6 and S0are generated can be determined.

By way of example, where the input terminal PT is at Middle level andthe switch Z1 is switches on, the phase difference detecting pulses S2and S0 are, as is the case with that shown in FIG. 4, generated during aD3±0.5, clock period at a reference timing which is two clock period ofD3 subsequent to the time at which U1 is rendered to be Low. Also, wherethe input terminal PT is at a High level and the switch Z0 is switchedon, as compared with that shown in FIG. 4, the phase differencedetecting pulses S2 and S0 are generated during a ±0.5 clock period ofD3 at a reference timing which is 1+0.5 clock period of D3 subsequent tothe time at which U1 is rendered to be Low. Also, where the inputterminal PT is at a Low level and the switch Z2 is switched on, ascompared with that shown in FIG. 4, the phase difference detectingpulses S2 and S0 are generated during a ±0.5 clock period of D3 at areference timing which is 2+0.5 clock period of D3 subsequent to thetime at which U1 is rendered to be Low. Although for the purpose ofbrevity reference has been made only to S2 and S0, a similar descriptioncan apply to S1, S3, S4, S5 and S6 which are generally generated atsimilar timings to those discussed in connection with S2 and S0.

Accordingly, where as hereinbefore discussed the power supply timing forthe driving coils relative to the counterelectromotive voltage in thedriving coils deviates from the optimum efficient point, the selectivesetting of the timing of generation of the pulses with the use of thepulse timing selecting means is effective to compensate for thedeviation wherefore the power supply timing for the driving coilsrelative to the counterelectromotive voltage can be caused to approachthe optimum efficient point.

The reset circuit 60 shown in FIG. 1 will now be described.

The reset circuit 60 is operable, when asynchronism occurs in the phasecontrolled loop at the time the power is turned on or by reason of, forexample, the constraint of the movable element, to initialize byclamping the output EAO of the difference amplifier 30 at the clampinglevel of the difference amplifier output clamping circuit 53 to assurethe phase-synchronized pull of the phase controlled loop, that is, thestart of the motor.

Hereinafter, the operation will be described specifically.

While the specific circuit construction of the reset circuit 60 is shownin FIG. 11, in the event of the occurrence of the asynchronism at thetime the power is turned on or in the phase controlled loop, the outputEAO of the difference amplifier 30 does not generally correspond withthe number of revolutions of the motor. At this time, EAO is increasingor decreasing according to the output PD of the phase differencedetector 20. Where EAO is in a tendency to decrease, the oscillatingfrequency f of the voltage controlled oscillator 40 will be a lowfrequency, while where EAO is in a tendency to be naturally initialized,but in a tendency which is to increase, a tendency reverse to thatduring the initialization occurs.

In such a case, EAO will soon be saturated, the imaginal shortcircuitbetween the input terminals of the operational amplifier 31 will not beestablished, and therefore, the voltage at the inverting input terminalof the operational amplifier will become of a value lower than thevoltage at the non-inverting input terminal thereof. This is detected bya comparator 680. In other words, an output transistor 685 of thecomparator 680 is so constructed as to be switched on when the abovedescribed imaginal shortcircuit will not establish, and, therefore, oncethe transistor 685 is switched on, a transistor 664 is switched off by alatch circuit 661 with the consequence being that an output transistor667 of the reset circuit 60 can be switched on. A collector output S ofthe output transistor 667 is connected with an S terminal of the phasedifference detector 20 shown in FIG. 5 and, therefore, when the outputtransistor 667 is switched on, the output PD will loose a currentabsorbing capability. Therefore, the output PD will have only a currentdischarging capability, causing the output EAO of the differenceamplifier 30 to drop. The drop of EAO continues until the differenceamplifier output clamping circuit 53 is operated and EAO is subsequentlyclamped. That is to say, when EAO is clamped, the transistor 55 conductsto relieve the transistor 664 from the OFF state caused by the latchcircuit 661, thereby switching the transistor 664 on. As a resultthereof, the output transistor 667 of the reset circuit 60 is switchedoff and the current absorbing capability of the output PD is recovered,with the initialization of EAO subsequently terminated.

In this way, the reset circuit 60 detects this when the output EAO ofthe difference amplifier 30 increases and is saturated, thereby loweringEAO while the output PD of the phase difference detector 20 is impartedonly the current discharging capability. On the other hand, at themoment EAO is clamped by the operation of the difference amplifieroutput clamping circuit 53, the current absorbing capability of PD isrecovered with the initialization of EAO terminated accordingly.

Accordingly, by the provision of the reset circuit 60, the output EAO ofthe difference amplifier 30 can be initialized and the motor can beassuredly started even when at the time the power is turned on or bysome other reason asynchronism occurs in the phase controlled loop.

According to the foregoing illustrated embodiment, by the provision ofthe so-called phase controlled loop (PLL loop) operable to control theoscillating frequency and the phase of the voltage controlled oscillatorby supplying an electric power through the motor driving coils on thebasis of the output of the voltage controlled oscillator at all times,then detecting the difference in phase between the power supply waveformand the counterelectromotive voltage in the driving coils with the useof the phase difference detector and controlling the phase difference tozero by the utilization of an amplified signal thereof, there is noinfluence brought about by the armature reaction and the motor can bedriven efficiently, yet, no filtering circuit hitherto required isrequired. Accordingly, a large capacitance capacitor can be considerablyreduced. Also, since the phase difference detector generates the phasedifference detecting pulses during the power supply interrupting periodfor the driving coils and equivalently provides the phase differenceoutput of the counterelectromotive voltage and the power supplyswitching signal by comparing the counterelectromotive voltage generatedin the driving coils and the neutral point voltage during the powersupply interrupting period for the driving coils, the timing thegeneration of the detecting pulse can be set so as to avoid the periodduring which spike noises tending to be generated immediately after thepower supply interrupting period for the driving coils and, therefore,any possible influence brought about by the spike noises can be avoided.Moreover, since the phase difference detection is carried out during thepower supply interrupting period, any possible voltage drop and itsvariation resulting from the power supply current generated during thepower supply period and the impedance of the driving coils will bring noadverse influence. In addition, since the width of the phase differencedetecting pulse generated during the power supply interrupting period isconstant relative to the electrical angle of the motor or the mechanicalangle and depends only on the duty of the comparison output between thecounterelectromotive voltage and the neutral point voltage during theperiod in which the phase difference detecting pulses are generated, thephase difference detecting gain does not vary under the influence of thenumber of revolutions of the motor and the phase controlled loop can beoperated in a stabilized manner at all times.

Also, in the illustrated embodiment, since the phase controlled loop forcontrolling the oscillating frequency and the phase of the voltagecontrolled oscillator is constructed such that the output of the voltagecontrolled oscillator can be supplied through the motor driving coilsand the phase difference between the power supply waveform and thecounterelectromotive voltage for the driving coils can be controlled tozero, the oscillating frequency of the voltage controlled oscillator othe output frequency of the frequency divider therefore assumes afrequency corresponding to the rotational speed of the motor when thephase controlled loop is in a pull state. Accordingly, as shown in FIG.1, it is possible to provide the speed signal output terminal 202 withthe motor speed signal through the transistor 200 which is selectivelyswitched on and off according to the output of the frequency divider.

Hereinafter, a second embodiment of the present invention will bedescribed with reference to the drawings.

FIG. 12 illustrates an essential portion of the circuit construction ofthe driving device for the brushless motor according to the secondembodiment of the present invention. It differs from the construction ofFIG. 1 in that a timing circuit 260 is employed, the structure otherthan the use of the timing device 260 being identical with the brushlessmotor driving device shown in FIG. 1.

Referring to an example of the construction of the timing circuit 260,and referring to FIG. 12, the output D4 of the frequency divider 41 isconnected to the base of a transistor 262 through a resistor 261. Avoltage divider comprised of resistors 263 and 264 is connected betweenthe stabilizing power source line Vreg and ground, a voltage dividingpoint J being connected to the base of a transistor 268 whose emitter isconnected to the base of a transistor 266. The transistors 266 and 267have their emitters connected together and also to the stabilizing powersource line Vreg through a constant current source 265. The base of thetransistor 267 is connected to the emitter of a collector-groundedtransistor 269. The transistors 266 and 267 have their collectorsconnected to respective collectors of transistors 270 and 271. The basesof the transistors 270 and 271 are connected together and also connectedto the collector of the transistor 270 while the emitters of thetransistors 270 and 271 are grounded. A capacitor 273 is connected inseries to a constant current source 272 between the stabilizing powersource line Vreg and ground. A junction K between the constant currentsource 272 and the capacitor 273 is connected to the base of thetransistor 269 and also with the emitter of a collector-groundedtransistor 274. The base of the transistor 274 is connected to thevoltage dividing point J. A common junction between the respectivecollectors of the transistors 267 and 271 is connected to the base ofthe transistor 275, and the emitter of the transistor 275 is connectedto the emitter of the transistor 262 and also to ground. Yet, thecollectors of the respective transistors 275 and 262 are connectedtogether and also to the stabilizing power source line Vreg through aresistor 276 and the base of a transistor 277. The transistor 277 hasits emitter connected to ground and its collector connected to thestabilizing power source line Vreg through a resistor 278 and also tothe speed signal output terminal 279.

The operation of the brushless motor driving device of the abovedescribed construction will now be described.

When a power source voltage Vcc is applied, the stabilizing power sourcestarts its operation with the stabilizing voltage Vreg generated and theentire circuit is therefore operated with the motor started. At thistime, when the stabilizing voltage Vreg is applied to the stabilizingpower source line, a constant voltage Vreg.R₆₄ /(R₆₃ +R₆₄) (wherein R₆₃and R₆₄ represent respective resistances of the resistor 263 and 264) isgenerated at the base of one transistor 268 forming a part of adifferential transistor pair, that is, the voltage dividing point Jbetween the resistors 263 and 264. On the other hand, the voltage at thebase of the other transistor 269 forming a part of the differentialtransistor pair, that is, the junction K, gradually increases with theprogress of the charging of the current from the constant current source272 on the capacitor 273. During a period in which the charging on thecapacitor 273 has not yet been proceeded subsequent to the applicationof the stabilizing voltage Vreg and, therefore, the voltage at the pointK is lower than the voltage at the point J, the transistors 267 and 266are switched on and off, respectively, and therefore, the transistor 275is switched on and the transistor 277 is kept in an off state at alltimes, with the consequence being that the speed signal output terminal279 remains at a High level. When after the passage of a predeterminedtime and consequent upon the progress of the charging on the capacitor273 the voltage at the point K becomes higher than the voltage at thepoint J, the transistors 267 and 266 are switched off and on,respectively, resulting in the transistor 276 being switched off and thetransistor 277 assuming a state which is reverse that of the transistor262. At this time, the transistor 262 is selectively switched on or offdepending on the High or Low state of the output D4 of the frequencydivider 41 and, in response to such a state, the transistor 277 isswitched off or on and, therefore, a rectangular wave signal in whichthe High and Low states are repeated in correspondence with the outputD4 of the frequency divider 41 is outputted from the speed signal outputterminal 279. As hereinabove described, the timing circuit 260 isconstructed so as to output a frequency signal corresponding to theoutput frequency of the frequency divider after the passage of thepredetermined time subsequent to the start of the motor.

As hereinbefore described, by the provision of the timing circuit 260,the frequency signal is outputted at the speed signal output terminal279 after the phase controlled loop for zeroing the phase differencebetween the power supply waveform for the motor and thecounterelectromotive voltage in the driving coils has been set in thepull state. In other words, during a transit condition that lastssubsequent to the start of the motor and before the phase controlledloop is brought in the pull state, no frequency signal will be outputtedto the speed signal output terminal 279. By so doing, since thefrequency corresponding to the oscillating frequency of the voltagecontrolled oscillator 40 or the output frequency of the frequencydivider 41 is synchronized with the motor speed after the passage of thepredetermined time subsequent to the start of the motor, that is, afterthe phase controlled loop has been brought in the pull state, the motorspeed signal can be obtained at the speed signal output terminal 279.

It is noted that, although in the embodiments shown in FIGS. 1 and 12the motor speed signal has been described as formed on the basis of theoutput of the frequency divider, arrangement may be made such that theoscillating frequency of the voltage controlled oscillator itself can beused as the speed signal.

Hereinafter, a speed control device for the brushless motor according toone embodiment of the present invention will be described with referenceto the drawings.

FIG. 13 illustrates the circuit construction of the speed control devicefor the brushless motor according to the embodiment of the presentinvention. In FIG. 13, the driving coils 1 to 3 are connected at theirone end to each other; the driving coil 1 is connected at the other endto the anode of a diode 4, the cathode of a diode 5 and the respectivecollectors of driving transistors 10 and 13; the driving coil 2 isconnected at the other end to the anode of a diode 6, the cathode of adiode 7 and the respective collectors of driving transistors 11 and 14;the driving coil 3 is connected at the other end to the anode of a diode8, the cathode of a diode 9 and the respective collectors of drivingtransistors 12 and 15; the respective cathodes of the diodes 4, 6 and 8and the respective emitters of the driving transistors 10, 11 and 12 areconnected to an output of a buffer circuit 1050; and the respectiveanodes of the diodes 5, 7 and 9 and the respective emitters of thetransistors 13, 14 and 15 are connected to ground. The base of each ofthe driving transistors 10 to 15 is connected to the output of a poweramplifier 43 having its input connected to the output of the logiccircuit 42. It is noted that the logic circuit 42 and the poweramplifier 42 together constitute the power supply switching circuit 44.The input of the logic circuit 42 is connected to the output D1 of thefrequency divider 41 which has its input connected to an output of areference signal generator 400. The other output D2 of the frequencydivider 41 and the outputs U1, U2, C1, V2, W1 and W2 from the logiccircuit 42 are inputted to the phase difference detecting pulsegenerator 28, and ends Uo, Vo and Wo of the respective driving coils 1,2 and 3 are inputted to buffer circuits 21, 22 and 23. The respectiveoutputs U_(B), V_(B) and W_(B) from the buffer circuits 21, 22 and 23are inputted to the comparator 27 and are connected together through theresistors 24, 25 and 26, the common junction N_(B) being inputted to thecomparator 27. The output PD of the comparator 27 is controlled by theoutput from the phase difference detecting pulse generator 28. It isnoted that the various component parts 21 to 28 constitute the phasedifference detector 20 while the output PD constitutes the output fromthe phase difference detector 20. The output PD from the phasedifference detector 20 is connected to the inverting input terminal ofthe operational amplifier 31 through the resistor 32, and the seriescircuit of resistor 33 and capacitor 34 and the capacitor 35 areconnected between the inverting input terminal of the operationalamplifier 31 and the output terminal thereof. The non-inverting inputterminal of the operational amplifier 31 is applied with thepredetermined bias voltage from the resistors 36 and 37. It is notedthat the various component parts 31 to 37 constitute the differenceamplifier 30 while an output EAO from the difference amplifier 30 isconnected to the input of the buffer circuit 1050.

It is noted that the various component parts 1 to 15, 20, 30, 41 and 44function in a manner identical with those in the brushless motor drivingdevice of FIG. 1 which are designated by like reference numerals.

With respect to the speed control device for the brushless motor of theabove described construction, the operation thereof will now bedescribed.

FIG. 14 is an explanatory diagram for explaining the principle ofoperation of the speed control device for the brushless motor accordingto the present invention, showing a phase relationship between a drivingcoil counterelectromotive voltage and a driving coil power supplywaveform. FIG. 14(a) illustrates the case in which the phaserelationship between the counterelectromotive voltage (dotted line) andthe power supply waveform (solid line) is optimum, whereas FIGS. 14(b)and 2(c) illustrate the respective cases wherein a displacement of aphase angle φ occurs from the optimum condition. In FIG. 13, the outputfrom the reference signal generator 400 is transmitted to the drivingcoils 1 to 3 through the frequency divider 41, the power supplyswitching circuit 44 and the driving transistors 10 to 15. Accordingly,the power supply waveforms for the driving coils 1 to 3 are synchronizedwith the output from the reference voltage generator 400. Also, thecounterelectromotive voltage in the driving coils 1 to 3 has itsfrequency and phase variable depending on the number of revolutions ofthe motor, and the number of revolutions of the motor is controlled bythe amount of electric power supplied to the driving coils, that is, theoutput from the buffer circuit 1050. Accordingly, by controlling thenumber of revolutions of the motor, that is, the frequency and phase ofthe counterelectromotive voltage in the driving coils on the basis ofthe output from the buffer circuit 1050, it is possible to control thedifference in phase between the power supply waveform for the drivingcoils synchronized with the output from the reference signal generator400 and the counterelectromotive voltage in the driving coils. In viewof this, if a phase control loop is provided with which, where as shownin FIGS. 14(b) and 2(c) the displacement of the phase angle φ occursbetween the driving coil counterelectromotive voltage and the drivingcoil power supply waveforms, the phase difference φ is detected by thephase difference detector 20 and then amplified by the differenceamplifier 30 and the output of the buffer circuit 1050 can be controlledso as to render φ to become zero, it is possible to secure the optimumpower supply condition shown in FIG. 14(a). Accordingly, it is possibleto steadily and efficiently generate a motor driving torque and themotor is thus driven and, at the same time, the control of the number ofrevolutions using the phase control is rendered possible.

The method of detecting the phase difference φ between the driving coilcounterelectromotive voltage and the driving coil power supply waveformhas already been described in connection with the brushless motordriving device and, therefore, the details thereof will not bereiterated.

According to the present invention as hereinbefore described, by theprovision of the phase controlled loop operable to supply the electricpower to the motor driving coils in synchronism with the output of thereference signal generator, to detect and amplify the phase difference φbetween the power supply waveform and the driving coilcounterelectromotive voltage by the use of the phase difference detectorand the difference amplifier, respectively, and to control, in responseto the amplified signal, the amount of the electric power supplied tothe driving coils on the basis of the output from the buffer circuit soas to render the phase difference φ to be zero, a brushless motor havingno position detector for detecting the position of movable element canbe efficiently driven in a stabilized manner and, at the same time, thecontrol of the number of revolutions using the phase control is renderedpossible.

It is noted that, although in FIG. 13 the amount of the electric powerto the driving coils 1 to 3 has been controlled by the buffer circuit1050, it may be possible to control it with a smoothened output obtainedthrough an inductance 1063 and a capacitor 1064 by comparing the outputEAO of the difference amplifier 30 with an output of a sawtooth wavegenerator 1060 as shown in FIG. 15 and switching a transistor 1062 independence on the comparison output. Also, as shown in FIG. 16, theoutput currents of the driving transistors 13 to 15 may be controlled independence on the output EAO of the difference amplifier 30 by use of abuffer circuit 1070, transistors 1071 to 1073 and a motor currentdetecting resistor 1074. While in the embodiment of the presentinvention the case is shown with a three-phase total wave drive system,a brushless motor driving device of a system similar to that of thepresent invention can be realized even in other drive systems, forexample, a two-phase total wave drive system, a two-phase half wavedrive system or a three-phase half wave drive system.

INDUSTRIAL APPLICABILITY

The brushless motor driving device of the present invention includes aplurality of phases of motor driving coils; a plurality of drivingtransistors connected with to the driving coils; a voltage controlledoscillator for outputting a signal having an appropriate frequency; apower supply switching circuit for forming a power supply switchingsignal for the driving coils on the basis of a frequency signalcorresponding to the frequency of oscillation of the voltage controlledoscillator; a phase difference detector having a comparator forgenerating a phase difference detecting pulse having a predeterminedphase relationship with the power supply switching signal during aperiod in which no electric power is supplied to the driving coils, andalso for comparing a counterelectromotive voltage generated in thedriving signals with a neutral point voltage of the driving coils duringa period in which the phase difference detecting pulse is generated, thephase difference detector being operable to detect an equivalent phasedifference between the power supply switching signal and thecounterelectromotive voltage in reference to an output from thecomparator; and a difference amplifier for amplifying an output from thephase difference detector and for generating an output which is in turnapplied to the voltage controlled oscillator. With this construction, itis possible to realize the excellent brushless motor drive device whichdoes not require the use of the hitherto required filtering circuit andis therefore capable of considerably reducing the use of a of highcapacitance capacitor and which is free from such problematic variationsresulting from the spike noises contained in the driving coil powersupply waveform and from the supplied power and the impedance of thedriving coils and a variation in power source voltage and load and,also, the lowering of the efficiency resulting from the armaturereaction. Also, by the provision of the lowest frequency settingcircuit, the oscillating frequency of the voltage controlled oscillatorcan be set to the lowest frequency at the time the power is turned on tothereby generate the revolving magnetic field at a sufficient speed forthe movable element to follow up so that the motor can be assuredlystarted. Yet, by the provision of the difference amplifier outputclamping circuit, the quick phase synchronism of the phase controlledloop is possible to assuredly start the motor by clamping the level ofthe difference amplifier output EAO at the level at which theoscillating frequency of the voltage controlled oscillator is increased.

Also, by the provision of the pulse timing selecting means, the timingat which the phase difference detecting pulses can be generated can bedetermined and, therefore, it is possible to render the timing at whichthe electric power is supplied to the driving coils relative to thecounterelectromotive voltage in the driving coils to approach theoptimum efficient point.

By the provision of the reset circuit, the difference amplifier outputcan be initialized even when the power is turned on or in the event ofthe occurrence of a deviation in synchronism of the phase controlledloop and, therefore, the motor can be assuredly started.

By the employment of the construction wherein the frequency signalcorresponding to the oscillating frequency of the voltage controlledoscillator or output frequency of the frequency divider operable todivide the oscillating frequency of the voltage controlled oscillator isoutputted as the speed signal, the motor speed detection is possiblewithout the employment of a speed detector, such as a hole element forthe speed detection, or without specially connecting a tachometer to themotor. Also, since an arrangement has been made such that the frequencysignal can be obtained from the voltage controlled oscillator or thefrequency divider therefor, the speed detecting frequency can besufficiently increased and, therefore, a highly accurate quick controlof a high response is possible where the speed control is desired.

In addition, by integrating into an IC, a brushless motor drive devicehaving an excellent performance and having an extremely minimized numberof externally fitted parts can be realized at reduced costs.

Moreover, by constructing the phase controlled loop so as to be operableto supply the electric power to the motor driving coils in synchronismwith the output of the reference signal generator, to detect and amplifythe phase difference φ between the power supply waveform and the drivingcoil counterelectromotive voltage by the use of the phase differencedetector and the difference amplifier, respectively, and to control, inresponse to the amplified signal as the torque commanding signal, theamount of the electric power supplied to the driving coils, a brushlessmotor having no position detector for detecting the position of themovable element can be efficiently driven in a stabilized manner and, atthe same time, the phase control of the number of revolutions of themotor is possible. Accordingly, by integrating together into an IC, thebrushless motor drive device extremely excellent in performance andhaving an extremely minimized number of externally fitted parts and,therefore, low in price and compact in size, yet, employing the controlof the number of revolutions based on the highly accurate phase controlcan be realized.

We claim:
 1. A brushless motor driving device comprising:a pluralitymotor driving coils of different phases; a plurality of drivingtransistors, coupled to said motor driving coils, for periodicallysupplying an electric power to said motor driving coils; a voltagecontrolled oscillator; a power supply switching means for generating apower supply switching signal for driving said motor driving coils onthe basis of a frequency signal corresponding to a frequency ofoscillation of said voltage controlled oscillator; a phase differencedetecting means for detecting a difference between the power supplyswitching signal and a counterelectromotive voltage generated in saidmotor driving coils during a period in which no electric power issupplied to said motor driving coils; a difference amplifying means foramplifying an output from the phase difference detecting means and foroutputting a thus amplified signal to said voltage controlledoscillator; and a pulse timing selected means for selecting a pulsetiming; said phase difference detecting means comprising a phasedifference detecting pulse generator for generating a phase differencedetecting pulse having a predetermined phase relationship with respectto the power supply switching signal at the pulse timing selected bysaid pulse timing selecting means, and a comparator for comparing, inresponse to an output pulse signal from the phase difference detectingpulse generator, the counterelectromotive voltage generated in saidmotor driving coils with a neutral point voltage of said motor drivingcoils.
 2. A brushless motor driving device comprising:a plurality motordriving coils of different phases; a plurality of driving transistors,coupled to said motor driving coils, for periodically supplying anelectric power to said motor driving coils; a power supply switchingmeans for sequentially transmitting a power supply switching signal tosaid motor driving transistors; a voltage controlled oscillator forapplying a signal of an appropriate frequency to said power supplyswitching means; a phase difference detecting means for detecting aphase difference between the power supply switching signal and acounterelectromotive voltage generated in said motor driving coilsduring a period in which no electric power is supplied to said motordriving coils; a difference amplifier for amplifying an output from thephase difference detecting means and for outputting a thus amplifiedsignal to said voltage controlled oscillator; a lowest frequency settingmeans for setting the lowest oscillating frequency of said voltagecontrolled oscillator; and, a difference amplifier output clamping meansfor clamping an output of said difference amplifier at a predeterminedlevel.
 3. A brushless motor driving device comprising:a plurality motordriving coils of different phases; a plurality of driving transistors,coupled to said motor driving coils, for periodically supplying anelectric power to said motor driving coils; a power supply switchingmeans for sequentially transmitting a power supply switching signal tosaid motor driving transistors; a voltage controlled oscillator forapplying a signal of an appropriate frequency to said power supplyswitching means; a phase difference detecting means for detecting aphase difference between the power supply switching signal and acounterelectromotive voltage generated in said motor driving coilsduring a period in which no electric power is supplied to said motordriving coils; a difference amplifier for amplifying an output from thephase difference detecting means and for outputting a thus amplifiedsignal to said voltage controlled oscillator; and a frequency dividerfor dividing the frequency of oscillation of the voltage controlledoscillator, an output from said frequency divider being supplied to thepower switching means, a frequency signal corresponding to one of thefrequency of oscillation of said voltage controlled oscillator and thefrequency of the output from said frequency divider being outputted as amotor speed signal.
 4. The brushless motor driving device as claimed inclaim 3, wherein one of said voltage controlled oscillator and saidfrequency divider has an output connected to a timing means foroutputting, after a predetermined time subsequent to a start-up of thebrushless motor, the frequency signal as the motor speed signal.
 5. Abrushless motor driving device comprising:a plurality of motor drivingcoils of different phases; a plurality of driving transistors, coupledto said motor driving coils, for supplying an electric power to saidmotor driving coils; a power supply switching means for sequentiallytransmitting a power supply switching signal for driving said motordriving coils to said driving transistors; a reference signal generatormeans for inputting a signal having an appropriate frequency to thepower supply switching circuit; a phase difference detector means fordetecting a phase difference between the counterelectromotive voltagegenerated in said motor driving coils and the power supply switchingsignal during an interruption of the supply of electric power to saidmotor driving coils; and, a difference amplifier for amplifying anoutput from said phase difference detector, an output of said differenceamplifier being used as a torque commanding signal.